LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.scanlSY_f_lib.ALL;
LIBRARY synopsys;

USE synopsys.attributes.ALL;
ENTITY scanlSY_f IS
PORT (
i : IN type_scanlSY_f_i;
o : OUT type_scanlSY_f_o;
clk : IN std_logic;
resetn : IN std_logic);
END scanlSY_f;

ARCHITECTURE Seq OF scanlSY_f IS
SIGNAL state, nextstate : type_scanlSY_f_state;
ATTRIBUTE state_vector : string;
ATTRIBUTE state_vector OF Seq : ARCHITECTURE IS "state";
BEGIN -- Seq

PROCESS (clk, resetn)
BEGIN -- PROCESS
IF resetn = ’0’ THEN -- asynchronous reset (active low)
state <= s0;
ELSIF clk’event AND clk = ’1’ THEN -- rising clock edge
state <= nextstate;
END IF;
END PROCESS;
PROCESS (i,state)
BEGIN -- PROCESS
nextstate <= f(i,state);
END PROCESS;
o <= nextstate;
END Seq;